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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13716-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90440G Series
MB90443G/F443G/V440G
s DESCRIPTION
The MB90440G series with FULL-CAN*2 and FLASH ROM is a line of general-purpose, Fujitsu 16-bit microcontrollers specially designed for automotive and industrial applications. Its main features are three on board CAN Interfaces (generic type) , which conform to V2.0 Part A and Part B, supporting very flexible message buffering. Thus, more functions than a normal full CAN approach is available. While inheriting the AT architecture of the F2MC*1 family, the instruction set for the F2MC-16LX CPU core incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90440G series has as on-chip 32-bit accumulator, which enables processing of long-word data. The peripheral resources integrated in the MB90440G series include; an 8/10-bit A/D converter, UARTs (SCI) , I/O extended serial interface, 8/16-bit PPG timer, input/output timer (input capture (ICU) , output compare (OCU) ) . *1 : F2MC stands for FUJITUS Flexible Microcontroller, a registered trademark of FUJITSU LIMITED. *2 : Controller Area Network (CAN) is a license of Robert Bosch GmbH..
s PACKAGE
100-pin Plastic QFP
FPT-100P-M06
MB90440G Series
s FEATURES
* Clock Internal PLL clock multiplication circuit Base oscillation divided into two or multiplied by one to four Minimum execution time : 62.5 ns (4 MHz oscillation, PLL clock multiplication multiplier = 4, VCC = 5.0 V) 32 kHz subsystem clock * Instruction set optimized for controller applications Supported data types : bit, byte, word, and long-word types Standard addressing modes : 23 types Singed multiplication/division and extended RET1 instructions 32-bit accumulator enhancing high-precision operations * Enhanced high level language (C) and multi-tasking support instructions Use of a system stack pointer Symmetrical instruction set and barrel shift instructions * Program patch function (for two address pointers) * Enhanced execution speed : 4 byte instruction queue * Enhanced interrupt function : 8 priority levels programmable and 34 causes * Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS) * Internal ROM size and type FLASH ROM : 128 Kbytes Internal RAM size : 6 Kbyte and 14 Kbyte (evaluation chip) * FLASH ROM Supports automatic programming function, Embedded Algorithm* Writing command/erase command/erase suspend and resume command Algorithms completion flag Hardwire reset vector to show the fixed boot code sector Can be erased by each sector Sector protection by external programming voltage * Low-power consumption (stand-by) modes Sleep mode (CPU operating clock stops) Stop mode (Main oscillation stops) CPU intermittent operation mode Watch mode Time-base timer mode * General-purpose I/O ports : 81 ports * Timers Watchdog timer : 1 channel 8/16-bit PPG timer : 8/16-bit x 4 channels 16-bit reload timer : 2 channels * : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
(Continued)
2
MB90440G Series
(Continued)
* 16-bit I/O timers 16-bit free-run timers : 1 channel 16-bit input capture : 8 channels 16-bit output compare : 4 channels * Extended I/O serial interfaces : 1 channel * UART0 Full-duplex, double-buffered (8 bit) Can be used for clock synchronous and asynchronous transfer (with start/stop bit) * UART1 (SCI) Full-duplex, double-buffered (8 bit) Can be used for clock synchronous and asynchronous serial transfer (extended I/O serial) * External interrupt inputs : 8 channels Extended intelligent I/O service (EI2OS) is started by external input and external interrupt generation module * Delayed interrupt generation module : interrupt request for task switching * 8/10 bit A/D converter : 8 channels 8/10-bit resolution selectable Can be started by external trigger input Conversion time : 6.12 s * FULL-CAN interface 3 channels Conform to V2.0 Part A and Part B Supports very flexible message buffering (mail-box and FIFO buffering can be mixed) * External bus interface : maximum 16 Mbyte address space
3
MB90440G Series
s PRODUCT LINEUP
The following table provides a quick outlook of the MB90440G Series Part number MB90443G MB90F443G (under development) Parameter CPU System clock ROM size RAM size Operating voltage range Temperature range Package Voltage dedicated for emulator*2 QFP100
*1
MB90V440G
F2MC-16LX CPU On-chip PLL clock multiplier (x1, x2, x3, x4, 1/2 when PLL stops) Minimum instruction execution time : 62.5 ns (4 MHz osc. PLL x4) Mask ROM 128 Kbytes 6 Kbytes Flash memory 128 Kbytes 6 Kbytes 5 V 10% -40 C to +105 C PGA-256 No External 14 Kbytes
UART0
Full duplex double buffer Supports clock asynchronous/synchronous (with start/stop bits) transfer Baud rate : 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous) 500 K/1 M/2 Mbps (synchronous) at System clock = 16 MHz Full duplex double buffer Asynchronized (start/stop bits synchronized) and CLK-synchronous communication Baud rate : 601 bps to 250 kbps (asynchronous) 31.25 kbps to 2 Mbps (synchronous) Transfer can be started from MSB or LSB Supports internal clock synchronized transfer and external clock synchronized transfer Supports positive-edge and negative-edge clock synchronization Baud rate : 31.25 K/62.5 K/125 K/500 K/1 M/2 Mbps at System clock = 16 MHz 10-bit or 8-bit resolution 8 input channels Conversion time : 6.12 s (per one channel) Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function Signals an interrupt during overflow Supports Timer Clear during a match with Output Compare (Channel 0) Operation clock freq. : fsys/22, fsys/24, fsys/26, fsys/28 (fsys = System clock freq.) Signals an interrupt during a match with 16-bit I/O Timer Four 16-bit compare registers A pair of compare registers can be used to generate an output signal
UART1 (SCI)
Serial IO
8/10 bit A/D Converter 16-bit Reload Timer (2 channels) 16-bit I/O Timer 16-bit Output Compare (4 channels)
(Continued)
4
MB90440G Series
(Continued) Part number
Parameter 16-bit Input Capture (8 channels)
MB90443G (under development)
MB90F443G
MB90V440G
Rising edge, falling edge or rising & falling edge sensitive Four 16-bit capture registers Signals an interrupt upon external event
Supports 8-bit and 16-bit operation modes Eight 8-bit reload counters Eight 8-bit reload registers for L pulse width 8/16-bit Eight 8-bit reload registers for H pulse width Programmable Pulse A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as Generator 8-bit prescaler plus 8-bit reload counter (4 channels) 4 output pins Operation clock frequency. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 s@fosc = 4 MHz (fsys = System clock frequency, fosc = Oscillation clock frequency) Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Supports prioritized 16 message buffers for data and ID Flexible configuration of acceptance filtering : Full bit compare / Full bit mask / Two partial bit masks Supports up to 1 Mbps Can be programmed edge detection or level detection The external access used selective 8-bit bus or 16-bit bus is available. (External bus mode) Virtually all external pins can be used as general purpose I/O All push-pull outputs and schmitt trigger inputs Bit-wise programmable as input/output or peripheral signal Sub-clock for low power operation Supports automatic programming, Embedded AlgorithmTM Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10,000 times Data retention time : 10 years Boot block configuration Erase can be performed on each block Block protection with external programming voltage
CAN Interface 3 channels :
External Interrupt (8 channels) External bus interface
I/O Ports 32 kHz Subclock
Flash Memory
*1 : Values with conditions such as the operating frequency (See section " ELECTRICAL CHARACTERISTICS") . *2 : DIP switch S2 when using emulation pad MB2145-507. The details are referred to hardware manual of MB2145-507.
5
MB90440G Series
s PIN ASSIGNMENT
(TOP VIEW)
P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SOT0 P41/SCK0 P42/SIN0 P43/SIN1 P44/SCK1 VCC P45/SOT1 P46/SOT2 P47/SCK2 C P50/SIN2 P51/INT4 P52/INT5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
6
P53/INT6 P54/INT7 P55/ADTG AVCC AVR+ AVRAVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P56/TIN0 P57/TOT0 MD0 MD1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
X0A X1A PA0/INT3 RST P97/RX1 P96/TX1 P95/INT2/RX0 P94/TX0 P93/RX2 P92/TX2 P91/INT1 P90/INT0 P87/TOT1 P87/TIN1 P85/OUT1 P84/OUT0 P83/PPG3 P82/PPG2 P81/PPG1 P80/PPG0 P77/OUT3/IN7 P76/OUT2/IN6 P75/IN5 P74/IN4 P73/IN3 P72/IN2 P71/IN1 P70/IN0 N.C. MD2
(FPT-100P-M06)
MB90440G Series
s PIN DESCRIPTION
Pin No. 82 83 80 79 77 52 Pin name X0 X1 X0A X1A RST N.C. P00 to P07 85 to 92 AD00 to AD07 P10 to P17 93 to 100 AD08 to AD15 P20 to P27 1 to 8 A16 to A23 P30 9 ALE P31 10 RD H H H H H Circuit type A (Oscillation) A (Oscillation) B Function High speed oscillator input pins Low speed oscillator input pins External reset request input not connected General I/O port with programmable pullup. This function is enabled in the single-chip mode. I/O pins for 8 lower bits of the external address/data bus. This function is enabled when the external bus is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode. I/O pins for 8 higher bits of the external address/data bus. This function is enabled when the external bus is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode. I/O pins of 8 bits for A16 to A23 ot the external address bus. This function is enabled when the external bus is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode. Address latch enable output pin. This function is enabled when the external bus is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode. Read strobe output pin for the data bus. This function is enabled when the external bus is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the WR/WRL pin output is disabled. H Write strobe output pin for the data bus. This function is enabled when the external bus is in enable mode and the WR/WRL pin output is enabled. WRL is used as a write-strobe output pin for 8 lower bits of the data bus in 16-bit access while WR is used as a writestrobe output pin for 8 bits of the data bus in 8-bit access. General I/O port with programmable pullup. This function is enabled in the single-chip mode or external bus 8-bit mode or when WRH pin output is disabled. H WRH Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH output pin is enabled.
P32 12 WRL WR
P33 13
(Continued)
7
MB90440G Series
Pin No.
Pin name P34
Circuit type
Function General I/O port with programmable pullup. This function is enabled in the single-chip mode or when hold function is disabled. Hold request input pin. This function is enabled when the external bus is in enable mode and the hold function is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode or when hold function is disabled. Hold acknowledge output pin. This function is enabled when the external bus is in enable mode and the hold function is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the external ready function is disabled. Ready input pin. This function is enabled when the external bus is in enable mode and the external ready function is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode or when CLK output is disabled. CLK output pin. This function is enabled when the external bus is in enable mode and CLK output is enabled. General I/O port. This function is enabled when serial data output of UART0 is disabled. Serial data output pin for UART0. This function is enabled when UART0 enables serial data output. General I/O port. This function is enabled when clock output of UART0 is disabled. Serial clock I/O pin for UART0. This function is enabled when UART0 enables serial clock output. General I/O port. This function is always enabled. Serial data input pin for UART0. Set the corresponding DDR register to input if this function is used. General I/O port. This function is always enabled. Serial data input pin for UART1. Set the corresponding DDR register to input if this function is used. General I/O port. This function is enabled when serial clock output of UART1 is disabled. Serial clock I/O pin for UART1. This function is enabled when UART1 enables serial clock output. General I/O port. This function is enabled when serial data output of UART1 is disabled. Serial data output pin for UART1. This function is enabled when UART1 enables serial data output.
14 HRQ P35 15 HAK
H
H
P36 16 RDY P37 17 CLK P40 18 SOT0 P41 19 SCK0 P42 20 SIN0 P43 21 SIN1 P44 22 SCK1 P45 24 SOT1 G G G G G G H H
(Continued)
8
MB90440G Series
Pin No.
Pin name P46
Circuit type
Function General I/O port. This function is enabled when the extended serial I/O interface disables serial data output.
25 SOT2
G
Serial data output pin for the extended serial I/O interface. This function is enabled when the extended serial I/O interface enables serial data output. General I/O port. This function is enabled when the extended serial I/O interface disables serial clock output.
P47 26 SCK2 P50 28 SIN2 P51 to P54 29 to 32 INT4 to INT7 P55 33 ADTG P60 to P63 38 to 41 AN0 to AN3 P64 to P67 43 to 46 AN4 to AN7 P56 47 TIN0 P57 48 TOT0 P70 to P75 53 to 58 IN0 to IN5 D D D E E D D D G
Serial clock I/O pin for the extended serial I/O interface. This function is enabled when the extended serial I/O interface enables serial clock output. General I/O port. This function is always enabled. Serial data input pin for the extended serial I/O interface. Set the corresponidng DDR register to input if this function is used. General I/O ports. This function is always enabled. External interrupt request input pins for INT4 to INT7. Set the corresponding DDR register to input if this function is used. General I/O port. This function is always enabled. External trigger input pin for the 8/10-bit A/D converter. Set the corresponding DDR register to input if this function is used. General I/O ports. The function is enabled when the analog input enable register specifies port. Analog input pins for the 8/10-bit A/D converter. This function is enabled when the analog input enable register specifies A/D. General I/O ports. The function is enabled when the analog input enable register specifies port. Analog input pins for the 8/10-bit A/D converter. This function is enabled when the analog input enable register specifies A/D. General I/O port. This function is always enabled. Event input pin for the 16-bit reload timers 0. Set the corresponding DDR register to input if this function is used. General I/O port. This function is enabled when the 16-bit reload timers 0 disables output. Output pin for the 16-bit reload timers 0. This function is enabled when the 16-bit reload timers 0 enables output. General I/O ports. This function is always enabled. Trigger input pins for input captures ICU0 to ICU5. Set the corresponding DDR register to input if this function is used.
(Continued)
9
MB90440G Series
Pin No.
Pin name P76 to P77 OUT2 to OUT3
Circuit type
Function General I/O ports. This function is enabled when the OCU disables output.
59 to 60
D
Event output pins for output compares OCU2 and OCU3. This function is enabled when the OCU enables output. Trigger input pins for input captures ICU6 and ICU7. Set the corresponiding DDR register to input and prohibit the OCU output if this function is used. General I/O ports. This function is enabled when 8/16-bit PPG timer disables waveform output. Output pins for 8/16-bit PPG timer. This function is enabled when 8/16-bit PPG timer enables waveform output. General I/O ports. This function is enabled when the OCU disables output. Event output pins for output compares OCU0 and OCU1. This function is enabled when the OCU enables output. General I/O port. This function is always enabled. Input pin for the 16-bit reload timers 1. Set the corresponding DDR register to input if this function is used. General I/O port. This function is enabled when the 16-bit reload timers 0 disables output. Output pin for the 16-bit reload timers 1. This function is enabled when the reload timers 1 enables output. General I/O ports. This function is always enabled. External interrupt request input pins for INT0 to INT3. Set the corresponding DDR register to input if this function is used. General I/O port. This function is enabled when CAN2 disables output. TX output pin for CAN2. This function is enabled when CAN2 enables output. General I/O port. This function is always enabled. RX input pin for CAN2 interface. When the CAN function is used, output from the other functions must be stopped. General I/O port. This function is enabled when CAN0 disables output. TX output pin for CAN0. This function is enabled when CAN0 enables output. General I/O port. This function is always enabled. External interrupt request input pin for INT2. Set the corresponding DDR register to input if this function is used. RX input pin for CAN0 interface. When the CAN function is used, output from the other functions must be stopped.
IN6 to IN7
P80 to P83 61 to 64 PPG0 to PPG3 P84 to P85 65 to 66 OUT0 to OUT1 P86 67 TIN1 P87 68 TOT1 P90 to P91 69 to 70 INT0 to INT1 P92 71 TX2 P93 72 RX2 P94 73 TX0 P95 74 INT2 RX0 D D D D D D D D D
(Continued)
10
MB90440G Series
(Continued) Pin No.
Pin name P96
Circuit type
Function General I/O port. This function is enabled when CAN1 disables output. TX output pin for CAN1. This function is enabled when CAN1 enables output. General I/O port. This function is always enabled. RX input pin for CAN1 interface. When the CAN function is used, output from the other functions must be stopped. General I/O port. This function is always enabled. External interrupt request input pin for INT2. Set the corresponding DDR register to input if this function is used.
75 TX1 P97 76 RX1 PA0 78 INT3
D
D
D
34 37 35 36 49 to 50 51 27 23, 84 11, 42 81
AVCC AVSS AVRH AVRL MD0 to MD1 MD2 C VCC VSS
Power supply pin for the A/D Converter. This power supply must be Power supply turned on or off while a voltage higher than or equal to AVCC is applied to VCC. Power supply Dedicated ground pin for the A/D Converter External reference voltage pin for the A/D Converter. This power Power supply supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AVCC. Power supply External reference voltage pin for the A/D Converter C F Input pins for specifying the operating mode. The pins must be directly connected to VCC or Vss. Input pin for specifying the operating mode. The pin must be directly connected to VCC or Vss. This is the power supply stabilization capacitor pin. It should be connected externally to an 0.1 F ceramic capacitor.
Power supply Voltage (5.0 V) input pin Power supply Voltage (0.0 V) input pin
s INPUT LEVELS
The input level of ports P00 to P37 can be selected to be either TTL- or CMOS - level. The initial setting is TTL - level. These settings are global for all P00 to P37, it is not possible to set different levels to each port. The input level of ports P40 to PA0 can be selected to be either CMOS- or AUTOMOTIVE - level. The initial setting is CMOS - level. This settings can be done for each port individually.
11
MB90440G Series
s I/O CIRCUIT TYPE
Circuit type Circuit Remarks * Oscillation feedback resistor : 1 M approx. (High speed oscillator) 10M approx. (Low speed oscillator)
osillation feedback resistor
X1, X1A
A
X0,X0A
Standby control signal
* CMOS hysteresis input . Pull-up resistor : 50 k approx. B
R (pull-up) R HYS
* CMOS hysteresis input C
R HYS
VCC P-ch
* CMOS level output * CMOS hysteresis input * Automotive hysteresis input (See " INPUT LEVELS".)
N-ch
D
R R CMOS HYS AUTOM. HYS
(Continued)
12
MB90440G Series
Circuit type
Circuit
Remarks * CMOS level output * CMOS hysteresis input * Automotive hysteresis input (See " INPUT LEVELS".) * Analog input
VCC P-ch
N-ch
E
P-ch Analog input N-ch R R CMOS HYS AUTOM. HYS
R
CMOS HYS
* CMOS hysteresis input * Pull-down resistor : 50 k approx. (except FLASH devices)
F
R (pull-down)
VCC P-ch
* CMOS level output * CMOS hysteresis input * Automotive hysteresis input (See " INPUT LEVELS".) * TTL input (FLASH devices in flash write mode only)
N-ch
G
R R R T CMOS HYS AUTOM. HYS TTL
(Continued)
13
MB90440G Series
(Continued) Circuit type
Circuit
Remarks * CMOS level output * CMOS hysteresis input * TTL hysteresis input (See " INPUT LEVELS".) * Programmable pullup resistor : 50 k approx.
VCC VCC
CNTL
P-ch
H
N-ch
R R T
CMOS HYS TTL
14
MB90440G Series
s HANDLING DEVICES
1. Preventing Latch-up
CMOS IC chips may suffer latch-up under the following conditions : (1) A voltage higher than VCC or lower than VSS is applied to an input or output pin. (2) A voltage higher than the rated voltage is applied to between VCC and Vss. (3) The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. Always take sufficient precautions in using semiconductor devices to avoid this possibility. Also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage (VCC) when the analog system power-supply is turned on and off.
2. Handling Unused Input Pins
Do not leave unused input pins open, as doing so may cause misoperation of the device or latch-up leading to permanent damage. Unused input pins should be pulled up or pulled down through at least 2 k resistance. Unused I/O pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins.
3. Use of the External Clock
To use the external clock, drive only the X0 pin and leave the X1 pin open. A diagram of how to use an external clock is shown below.
MB90440G Series X0
open
X1
4. Precautions for when not using a Sub Clock Signal
If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leave the X1A pin open.
5. Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pins near the device.
VCC VSS
VCC VSS VCC MB90440G Series
VSS
VCC VSS
VSS
VCC
15
MB90440G Series
6. Pull-up/down resistors
The MB90440G Series does not support internal pull-up/down resistors (except pull-up resistors of port 0 to port 3) . Use external components needed.
7. Crystal Oscillator Circuit
Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via the shortest distances from X0 and X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the operation.
8. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D and D/A converters power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning on the digital power supply (VCC) . Turn off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that AVRH does not exceed AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) .
9. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D and D/A converters to AVCC = VCC, AVSS = AVRH = VSS.
10. N.C. Pin
The N.C. (internally connected) pin must be opened for use.
11. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more (0.2 V to 2.7 V) .
12. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, please turn on the power again.
13. Using REALOS
The use of (EI2OS) is not possible with the REALOS real time operation system.
14. Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the freerunning frequency of the automatic oscillating circuit in the PLL circuitly even if the oscillator is out of place or the clock input is stopped. Performance of this operation, however, cannot be guaranteed.
16
MB90440G Series
s BLOCK DIAGRAM
X0, X1 X0A, X1A RST Clock Controller F2MC 16LX CPU
RAM 6 K
16 bit I/O Timer 16 bit Input Capture 8 ch
IN0 to IN5 IN6/OUT2, IN7/OUT3 OUT0, OUT1
ROM 128 K
16 bit Output Compare 4 ch
Prescaler 8/16-bit PPG Timer 4 ch
SOT0 SCK0 SIN0 UART0
PPG0 to PPG3
Prescaler
CAN Controller 3 ch
RX0 to RX2 TX0 to TX2
SOT1 SCK1 SIN1 UART1 (SCI) 16-bit Reload Timer 2 ch TIN0, TIN1 TOT0, TOT1
Prescaler F 2 MC-16 Bus AD00 to AD15 A16 to A23 ALE RD External Bus Interface 10-bit ADC 8 ch WRL/WR WRH HRQ HAK RDY CLK
SCK2 SOT2 SIN2 Serial I/O
AVCC AVSS AN0 to AN7 AVRH AVRL ADTG
External Interrupt Circuit 8 ch
INT0 to INT7
17
MB90440G Series
s MEMORY MAP
MB90V440G MB90F443G/ MB90443G (under development)
FFFFFFH ROM (FF bank) FF0000H FEFFFFH ROM (FE bank) FE0000H FDFFFFH ROM (FD bank) FD0000H FCFFFFH ROM (FC bank) FC0000H External Access Memory 00FFFFH 004000H 003FFFH 003900H 0038FFH 001FF5H 001FF0H RAM 14 K 000100H 0000BFH 000000H External Access Memory Peripheral 000100H External Access Memory 0000BFH 000000H Peripheral RAM 6 K ROM correction ROM (Image of FF bank) Peripheral 003900H 002000H 0018FFH External Access Memory 00FFFFH 004000H 003FFFH ROM (Image of FF bank) Peripheral External Access Memory FE0000H FF0000H FEFFFFH ROM (FE bank) ROM (FF bank)
FFFFFFH
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same address, the table in ROM can be referenced without using the far specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM. The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00. The image between FF4000H and FFFFFFH is visible in bank 00, while the image between FF4000H and FFFFFFH is visible only in bank FF. Thus, it is recommended that the ROM data table be stored in the area of FF4000H and FFFFFFH .
18
MB90440G Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH to 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Analog input enable register Port 0 pullup control register Port 1 pullup control register Port 2 pullup control register Port 3 pullup control register Serial mode control register 0 Serial status register 0 Serial input/output data register 0 Rate and data register 0 Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Port input levels select register CAN2 RX/TX pin switching register Abbreviation PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PILR CANSWR Reserved DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ADER PUCR0 PUCR1 PUCR2 PUCR3 UMC0 USR0 UIDR0/UODR0 URD0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W UART0 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 6, A/D Port 0 Port 1 Port 2 Port 3 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B _______0B 11111111B 00000000B 00000000B 00000000B 00000000B 00000100B 00010000B XXXXXXXXB 0000000XB Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Ports CAN1/2 Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB _______XB 00000000B ______00B
(Continued)
19
MB90440G Series
Address 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H
Register Serial mode register 1 Serial control register 1 Serial input/output data register 1 Serial status register 1 UART1 prescaler control register Serial edge selection registor Serial I/O prescaler Serial mode control register Serial mode control register Serial Data register Serial edge selection registor 2 External interrupt enable register External interrupt request register External request level setting register A/D control status register 0 A/D control status register 1 A/D data register 0 A/D data register 1 PPG0 operation mode control register PPG1 operation mode control register PPG0 and PPG1 clock selection register PPG2 operation mode control register PPG3 operation mode control register PPG2 and PPG3 clock selection register PPG4 operation mode control register PPG5 operation mode control register PPG4 and PPG5 clock selection register
Abbreviation SMR1 SCR1 SIDR1/SODR1 SSR1 U1CDCR SES1 Reserved SCDCR SMCS SMCS SDR SES2 ENIR EIRR ELVR ADCS0 ADCS1 ADCR0 ADCR1 PPGC0 PPGC1 PPG01 Reserved PPGC2 PPGC3 PPG23 Reserved PPGC4 PPGC5 PPG45 Reserved
Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial value 00000000B 00000100B XXXXXXXXB 00001_00B 0___1111B _______0B 0___1111B ____0000B
UART1
Serial I/O
00000010B XXXXXXXXB _______0B 00000000B
External interrupt circuit
XXXXXXXXB 00000000B 00000000B 00000000B 00000000B XXXXXXXXB 00001_XXB 0_000__1B 0_000001B 000000__B 0_000__1B 0_000001B 000000__B 0_000__1B 0_000001B 000000__B
A/D converter
16-bit Programable Pulse Generator 0/1
16-bit Programable Pulse Generator 2/3
16-bit Programable Pulse Generator 4/5
(Continued)
20
MB90440G Series
Address 44H 45H 46H 47H to 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH to 6BH 6CH 6DH 6EH 6FH 70H to 7FH 80H to 8FH 90H to 9DH 9EH
Register PPG6 operation mode control register PPG7 operation mode control register PPG6 and PPG7 clock selection register
Abbreviation PPGC6 PPGC7 PPG67 Reserved
Read/ Write R/W R/W R/W
Resource name 16-bit Programable Pulse Generator 6/7 Input capture 0/1 Input capture 2/3 Input capture 4/5 Input capture 6/7 16-bit reload timer 0
Initial value 0_000__1B 0_000001B 000000__B
Input capture control status 0/1 Input capture control status 2/3 Input capture control status 4/5 Input capture control status 6/7 Timer control status register 0 Timer register 0/reload register 0 Timer control status register 1 Timer register 1/Reload register 1 Output compare control status register 0 Output compare control status register 1 Output compare control status register 2 Output compare control status register 3
ICS01 ICS23 ICS45 ICS67 TMCSR0 TMR0/ TMRLR0 TMCSR1 TMR1/ TMRLR1 OCS0 OCS1 OCS2 OCS3
R/W R/W R/W R/W R/W R/W R/W
00000000B 00000000B 00000000B 00000000B 00000000B ____0000B XXXXXXXXB XXXXXXXXB 00000000B ____0000B XXXXXXXXB XXXXXXXXB 0000__00B ___00000B 0000__00B ___00000B 00000000B
16-bit reload timer 1 R/W R/W R/W R/W R/W Output compare 0/1 Output compare 2/3
Reserved for CAN 2 Interface Timer data register Timer control status register ROM mirror function selection register TCDT TCCS ROMM R/W R/W R/W ROM mirror function selection module I/O timer 00000000B 00000000B _______1B
Reserved for CAN 0 Interface Reserved for CAN 1 Interface Prohibited area Program address detection control status register PACSR R/W Address match detection function Delayed interrupt generation module 00000000B
9FH
Delayed interrupt/release register
DIRR
R/W
_______0B
(Continued)
21
MB90440G Series
Address
Register Low-power consumption mode control register
Abbreviation
Read/ Write R/W
Resource name Low power consumption (stand-by) mode Low power consumption (stand-by) mode
Initial value
A0H
LPMCR
00011000B
A1H A2H to A4H A5H A6H A7H A8H A9H AAH ABH to ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH COH to FFH 22
Clock selection register
CKSCR Prohibited area
R/W
11111100B
Automatic ready function select register External address output control register Bus control signal selection register Watchdog timer control register Time base timer control register Watch timer control register Flash memory control status register (Flash only, otherwise reserved) Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15
ARSR HACR ECSR WDTC TBTC WTC Prohibited area FMCS Prohibited area ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 External
W W W R/W R/W R/W Watchdog timer Time base timer Watch timer External bus pin
0011__00B 00000000B 0000000_B XXXXX111B 1- -00100B 1X000000B
R/W
Flash Memory
000X0000B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller
00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B
(Continued)
MB90440G Series
(Continued)
Address 1FF0H 1FF1H 1FF2H 1FF3H 1FF4H 1FF5H Program address detection register 1 PADR1 Program address detection register 0 PADR0 Register Abbreviation Read/ Write R/W R/W R/W R/W R/W R/W Address match detection function Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Address 3900H 3901H 3902H 3903H 3904H 3905H 3906H 3907H 3908H 3909H 390AH 390BH 390CH 390DH 390EH 390FH 3910H to 3917H 3918H 3919H 391AH 391BH 391CH 391DH 391EH 391FH
Register Reload register L Reload register H Reload register L Reload register H Reload register L Reload register H Reload register L Reload register H Reload register L Reload register H Reload register L Reload register H Reload register L Reload register H Reload register L Reload register H
Abbreviation PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PRLL4 PRLH4 PRLL5 PRLH5 PRLL6 PRLH6 PRLL7 PRLH7 Reserved
Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial value XXXXXXXXB
16-bit programable pulse generator 0/1
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
16-bit programable pulse generator 2/3
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
16-bit programable pulse generator 4/5
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
16-bit programable pulse generator 6/7
XXXXXXXXB XXXXXXXXB XXXXXXXXB
Input capture register 0 Input capture register 0 Input capture register 1 Input capture register 1 Input capture register 2 Input capture register 2 Input capture register 3 Input capture register 3
IPCP0 IPCP0 IPCP1 IPCP1 IPCP2 IPCP2 IPCP3 IPCP3
R R R R R R R R Input captue 2/3 Input captue 0/1
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
(Continued)
23
MB90440G Series
(Continued)
Address 3920H 3921H 3922H 3923H 3924H 3925H 3926H 3927H 3928H 3929H 392AH 392BH 392CH 392DH 392EH 392FH 3930H to 39FFH 3A00H to 3AFFH 3B00H to 3BFFH 3C00H to 3CFFH 3D00H to 3DFFH 3E00H to 3EFFH 3F00H to 3FFFH Register Input capture register 4 Input capture register 4 Input capture register 5 Input capture register 5 Input capture register 6 Input capture register 6 Input capture register 7 Input capture register 7 Output compare register 0 Output compare register 0 Output compare register 1 Output compare register 1 Output compare register 2 Output compare register 2 Output compare register 3 Output compare register 3 Abbreviation IPCP4 IPCP4 IPCP5 IPCP5 IPCP6 IPCP6 IPCP7 IPCP7 OCCP0 OCCP0 OCCP1 OCCP1 OCCP2 OCCP2 OCCP3 OCCP3 Reserved Reserved for CAN 0 Interface Reserved for CAN 0 Interface Reserved for CAN 1 Interface Reserved for CAN 1 Interface Reserved for CAN 2 Interface Reserved for CAN 2 Interface Read/ Write R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Output compare 2/3 Output compare 0/1 Input captue 6/7 Input captue 4/5 Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
* Meaning of abbreviations used for reading and writing R/W : Read and Write enabled R : Read only W : Write only * Explanation of initial values 0 : The bit is initialized to 0. 1 : The bit is initialized to 1. X : The initial value of the bit is undefined. _ : The bit is not used. Its initial value is undefined. Note : Addresses in the range 0000H to 00FFH, which are not listed in the table, are reserved for the primary functions of the MCU. A read access to these reserved addresses results reading "X" and any write access should not be performed. 24
MB90440G Series
s CAN CONTROLLER
The MB90440G series contains three generic CAN controllers (CAN0, CAN1, CAN2) . The CAN controller has the following features : * Conforms to CAN Specification Version 2.0 Part A and B - Supports transmission/reception in standard frame and extended frame formats * Supports transmission of data frames by receiving remote frames * 16 transmission/reception message buffers - 29-bit ID and 8-byte data - Multi-level message buffer configuration * Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID acceptance mask - Two acceptance mask registers in either standard frame format or extended frame formats * Bit rate programmable from 10 Kbps to 1 Mbps (when input clock is at 16 MHz) List of Control Registers Address CAN0 CAN1 CAN2 000070H 000080H 00005CH 000071H 000081H 00005DH 000072H 000082H 00005EH 000073H 000083H 000074H 000084H 000075H 000085H 000076H 000086H 000077H 000087H 000078H 000088H 000079H 000089H 00005FH 000060H 000061H 000062H 000063H 000064H 000065H Register Message buffer valid register Transmit request register Transmit cancel register Transmit complete register Receive complete register Remote request receiving register Receive overrun register Receive interrupt enable register Control status register Last event indicator register Receive/transmit error counter Abbreviation BVALR TREQR TCANR TCR RCR RRTRR ROVRR RIER CSR LEIR RTEC Read/ Write R/W R/W W R/W R/W R/W R/W R/W R/W, R R/W R Initial Value 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00---000 0----01B -------- 0000000B 00000000 00000000B
00007AH 00008AH 000066H 00007BH 00008BH 000067H 00007CH 00008CH 000068H 00007DH 00008DH 000069H 00007EH 00008EH 00006AH 00007FH 00008FH 00006BH 003B00H 003D00H 003F00H 003B01H 003D01H 003F01H 003B02H 003D02H 003F02H 003B03H 003D03H 003F03H 003B04H 003D04H 003F04H 003B05H 003D05H 003F05H
(Continued)
25
MB90440G Series
(Continued)
Address CAN0 CAN1 CAN2 003F06H 003F07H 003F08H 003F09H 003B06H 003D06H 003B07H 003D07H 003B08H 003D08H 003B09H 003D09H Register Bit timing register IDE register Transmit RTR register Abbreviation BTR IDER TRTRR RFWTR TIER Read/ Write R/W R/W R/W R/W R/W Initial Value -1111111 11111111B XXXXXXXX XXXXXXXXB 00000000 00000000B XXXXXXXX XXXXXXXXB 00000000 00000000B XXXXXXXX XXXXXXXXB AMSR R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB Acceptance mask register 0 AMR0 R/W XXXXX--XXXXXXXXB XXXXXXXX XXXXXXXXB Acceptance mask register 1 AMR1 R/W XXXXX--XXXXXXXXB
003B0AH 003D0AH 003F0AH 003B0BH 003D0BH 003F0BH
003B0CH 003D0CH 003F0CH Remote frame receive waiting register 003B0DH 003D0DH 003F0DH 003B0EH 003D0EH 003F0EH 003B0FH 003D0FH 003F0FH 003B10H 003D10H 003B11H 003D11H 003B12H 003D12H 003B13H 003D13H 003B14H 003D14H 003B15H 003D15H 003B16H 003D16H 003B17H 003D17H 003B18H 003D18H 003B19H 003D19H 003F10H 003F11H 003F12H 003F13H 003F14H 003F15H 003F16H 003F17H 003F18H 003F19H Acceptance mask select register Transmit interrupt enable register
003B1AH 003D1AH 003F1AH 003B1BH 003D1BH 003F1BH
26
MB90440G Series
List of Message Buffers (ID Registers) Address CAN0 CAN1 CAN2 003A00H 003C00H 003E00H to to to 003A1FH 003C1FH 003E1FH 003A20H 003C20H 003E20H 003A21H 003C21H 003E21H 003A22H 003C22H 003E22H 003A23H 003C23H 003E23H 003A24H 003C24H 003E24H 003A25H 003C25H 003E25H 003A26H 003C26H 003E26H 003A27H 003C27H 003E27H 003A28H 003C28H 003E28H 003A29H 003C29H 003E29H 003A2AH 003C2AH 003E2AH 003A2BH 003C2BH 003E2BH 003A2CH 003C2CH 003E2CH 003A2DH 003C2DH 003E2DH 003A2EH 003C2EH 003E2EH 003A2FH 003C2FH 003E2FH 003A30H 003C30H 003E30H 003A31H 003C31H 003E31H 003A32H 003C32H 003E32H 003A33H 003C33H 003E33H 003A34H 003C34H 003E34H 003A35H 003C35H 003E35H 003A36H 003C36H 003E36H 003A37H 003C37H 003E37H 003A38H 003C38H 003E38H 003A39H 003C39H 003E39H 003A3AH 003C3AH 003E3AH 003A3BH 003C3BH 003E3BH ID register 6 IDR6 R/W XXXXX--XXXXXXXXB ID register 5 IDR5 R/W XXXXX--XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 4 IDR4 R/W XXXXX--XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 3 IDR3 R/W XXXXX--XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 2 IDR2 R/W XXXXX--XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 1 IDR1 R/W XXXXX--XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 0 IDR0 R/W XXXXX--XXXXXXXXB XXXXXXXX XXXXXXXXB Register Abbreviation Read/ Write R/W Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXX XXXXXXXXB
RAM area
(Continued)
27
MB90440G Series
Address CAN0 CAN1 CAN2 003A3CH 003C3CH 003E3CH 003A3DH 003C3DH 003E3DH 003A3EH 003C3EH 003E3EH 003A3FH 003C3FH 003E3FH 003A40H 003C40H 003E40H 003A41H 003C41H 003E41H 003A42H 003C42H 003E42H 003A43H 003C43H 003E43H 003A44H 003C44H 003E44H 003A45H 003C45H 003E45H 003A46H 003C46H 003E46H 003A47H 003C47H 003E47H 003A48H 003C48H 003E48H 003A49H 003C49H 003E49H 003A4AH 003C4AH 003E4AH 003A4BH 003C4BH 003E4BH 003A4CH 003C4CH 003E4CH 003A4DH 003C4DH 003E4DH 003A4EH 003C4EH 003E4EH 003A4FH 003C4FH 003E4FH 003A50H 003C50H 003E50H 003A51H 003C51H 003E51H 003A52H 003C52H 003E52H 003A53H 003C53H 003E53H 003A54H 003C54H 003E54H 003A55H 003C55H 003E55H 003A56H 003C56H 003E56H 003A57H 003C57H 003E57H 003A58H 003C58H 003E58H 003A59H 003C59H 003E59H 003A5AH 003C5AH 003E5AH 003A5BH 003C5BH 003E5BH
Register
Abbreviation
Read/ Write
Initial Value XXXXXXXX XXXXXXXXB
ID register 7
IDR7
R/W XXXXX--XXXXXXXXB XXXXXXXX XXXXXXXXB
ID register 8
IDR8
R/W XXXXX--XXXXXXXXB XXXXXXXX XXXXXXXXB
ID register 9
IDR9
R/W XXXXX--XXXXXXXXB XXXXXXXX XXXXXXXXB
ID register 10
IDR10
R/W XXXXX--XXXXXXXXB XXXXXXXX XXXXXXXXB
ID register 11
IDR11
R/W XXXXX--XXXXXXXXB XXXXXXXX XXXXXXXXB
ID register 12
IDR12
R/W XXXXX--XXXXXXXXB XXXXXXXX XXXXXXXXB
ID register 13
IDR13
R/W XXXXX--XXXXXXXXB XXXXXXXX XXXXXXXXB
ID register 14
IDR14
R/W XXXXX--XXXXXXXXB
(Continued)
28
MB90440G Series
(Continued)
Address CAN0 CAN1 CAN2 003A5CH 003C5CH 003E5CH 003A5DH 003C5DH 003E5DH 003A5EH 003C5EH 003E5EH 003A5FH 003C5FH 003E5FH List of Message Buffers (DLC Registers and Data Registers) Address CAN0 CAN1 CAN2 003A60H 003C60H 003E60H 003A61H 003C61H 003E61H 003A62H 003C62H 003E62H 003A63H 003C63H 003E63H 003A64H 003C64H 003E64H 003A65H 003C65H 003E65H 003A66H 003C66H 003E66H 003A67H 003C67H 003E67H 003A68H 003C68H 003E68H 003A69H 003C69H 003E69H 003A6AH 003C6AH 003E6AH 003A6BH 003C6BH 003E6BH 003A6CH 003C6CH 003E6CH 003A6DH 003C6DH 003E6DH 003A6EH 003C6EH 003E6EH 003A6FH 003C6FH 003E6FH 003A70H 003C70H 003E70H 003A71H 003C71H 003E71H 003A72H 003C72H 003E72H 003A73H 003C73H 003E73H 003A74H 003C74H 003E74H 003A75H 003C75H 003E75H 003A76H 003C76H 003E76H 003A77H 003C77H 003E77H Register DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 DLC register 8 DLC register 9 DLC register 10 DLC register 11 Abbreviation DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DLCR8 DLCR9 DLCR10 DLCR11 Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ID register 15 IDR15 R/W XXXXX--XXXXXXXXB Register Abbreviation Read/ Write Initial Value XXXXXXXX XXXXXXXXB
(Continued)
29
MB90440G Series
Address CAN0 CAN1 CAN2 003A78H 003C78H 003E78H 003A79H 003C79H 003E79H 003A7AH 003C7AH 003E7AH 003A7BH 003C7BH 003E7BH 003A7CH 003C7CH 003E7CH 003A7DH 003C7DH 003E7DH 003A7EH 003C7EH 003E7EH 003A7FH 003C7FH 003E7FH 003A80H 003C80H 003E80H to to to 003A87H 003C87H 003E87H 003A88H 003C88H 003E88H to to to 003A8FH 003C8FH 003E8FH 003A90H 003C90H 003E90H to to to 003A97H 003C97H 003E97H 003A98H 003C98H 003E98H to to to 003A9FH 003C9FH 003E9FH 003AA0H 003CA0H 003EA0H to to to 003AA7H 003CA7H 003EA7H 003AA8H 003CA8H 003EA8H to to to 003AAFH 003CAFH 003EAFH 003AB0H 003CB0H 003EB0H to to to 003AB7H 003CB7H 003EB7H
Register DLC register 12 DLC register 13 DLC register 14 DLC register 15
Abbreviation DLCR12 DLCR13 DLCR14 DLCR15
Read/ Write R/W R/W R/W R/W
Initial Value ----XXXXB ----XXXXB ----XXXXB ----XXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB
Data register 0 (8 bytes)
DTR0
R/W
Data register 1 (8 bytes)
DTR1
R/W
Data register 2 (8 bytes)
DTR2
R/W
Data register 3 (8 bytes)
DTR3
R/W
Data register 4 (8 bytes)
DTR4
R/W
Data register 5 (8 bytes)
DTR5
R/W
Data register 6 (8 bytes)
DTR6
R/W
(Continued)
30
MB90440G Series
(Continued)
Address CAN0 CAN1 CAN2 003AB8H 003CB8H 003EB8H to to to 003ABFH 003CBFH 003EBFH 003AC0H 003CC0H 003EC0H to to to 003AC7H 003CC7H 003EC7H 003AC8H 003CC8H 003EC8H to to to 003ACFH 003CCFH 003ECFH 003AD0H 003CD0H 003ED0H to to to 003AD7H 003CD7H 003ED7H 003AD8H 003CD8H 003ED8H to to to 003ADFH 003CDFH 003EDFH 003AE0H 003CE0H 003EE0H to to to 003AE7H 003CE7H 003EE7H 003AE8H 003CE8H 003EE8H to to to 003AEFH 003CEFH 003EEFH 003AF0H to 003AF7H 003CF0H to 003CF7H 003EF0H to 003EF7H Register Abbreviation Read/ Write R/W Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB
Data register 7 (8 bytes)
DTR7
Data register 8 (8 bytes)
DTR8
R/W
Data register 9 (8 bytes)
DTR9
R/W
Data register 10 (8 bytes)
DTR10
R/W
Data register 11 (8 bytes)
DTR11
R/W
Data register 12 (8 bytes)
DTR12
R/W
Data register 13 (8 bytes)
DTR13
R/W
Data register 14 (8 bytes)
DTR14
R/W
003AF8H 003CF8H 003EF8H to to to 003AFFH 003CFFH 003EFFH
Data register 15 (8 bytes)
DTR15
R/W
31
MB90440G Series
s INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause Reset INT9 instruction Exception processing CAN 0 Receive CAN 0 Transmit/Node status CAN 1 Receive CAN 1 Transmit/Node status External interrupt (INT0/INT1) Timebase timer 16-bit reload timer 0 8/10-bit A/D converter Input/output timer External interrupt (INT2/INT3) Serial I/O 8/16-bit PPG timer 0/1/2/3 Input capture 0 External interrupt (INT4/INT5) CAN 2 Receive CAN 2 Transmit/Node status External interrupt (INT6/INT7) Monitoring timer Input capture 1 Input capture 2/3 8/16-bit PPG timer 4/5/6/7 Output compare 0 Output compare 1 Input capture 4/5 Output compare 2/3-input capture 6/7 16-bit reload timer 1 UART 0 Receive UART 0 Transmit UART 1 Receive UART 1 Transmit EI2OS support N/A N/A N/A N/A N/A N/A N/A *1 N/A *1 *1 N/A *1 *1 N/A *1 *1 N/A N/A *1 N/A *1 *1 N/A *1 *1 *1 *1 *1 *2 *1 *2 *1 Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH Interrupt control register Number ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH
(Continued)
32
MB90440G Series
(Continued)
Interrupt cause Flash memory Delayed interrupt generation module *1 *2 EI2OS support N/A N/A Interrupt vector Number #41 #42 Address FFFF58H FFFF54HH Interrupt control register Number ICR15 Address 0000BFH
: The interrupt request flag is cleared by the EI2OS interrupt clear signal. : The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available.
Notes : * N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal. * For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the EI2OS interrupt clear signal. * At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the first event. So it is recommended not to use the EI2OS for this interrupt number. * If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt causes share the same EI2OS descriptor which should be unique for each interrupt cause. For this reason, when one interrupt cause uses the EI2OS, the other interrupt should be disabled.
33
MB90440G Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol VCC Power supply voltage AVCC AVRH, AVRL Input voltage Output voltage Maximum clamp current Total maximum clamp current "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature VI VO ICLAMP ICLAMP IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 - 2.0 -40 -55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 Unit V V V V V mA mA mA mA mA mA mA mA mA mA mW mW C C
*5 *5 *3 *4
(VSS = AVSS = 0.0 V) Remarks
VCC = AVCC *1 AVCC AVRH / AVRL, AVRH AVRL*1
*2 *2 *6 *6 *3 *4
+ 2.0
20 15 4 100 50 -15 -4 -100 -50 500 400
MB90F443G MB90F443G (under development)
+ 105 + 150
*1 : AVCC, AVRH, and AVRL shall never exceed VCC. AVRH, AVRL shall never exceed AVCC. Also, AVRL shall never exceed AVRH. *2 : VI and VO shall never exceed VCC + 0.3 V. VI shall never exceed the specified ratings. However if the maximum current to/ from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *3 : Maximum output current specifies the peak value of the corresponding pin. *4 : The average output current specifies the average current of corresponding pins within 100 ms. (operation current x operation rate = average value) *5 : The total average output current specifies the average current of all corresponding pins within 100 ms. (operation current x operation rate = average value) *6 : * Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 * Use within recommended operating conditions. * Use at DC voltage (current) . (Continued) 34
MB90440G Series
(Continued)
* The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. * Sample recommended circuits. * Input/Output equivalent circuits
Protective diode
Vcc
Limiting resistance +B input (0 V to 16 V)
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
35
MB90440G Series
2. Recommended Operating Conditions
Parameter Symbol VCC, AVCC CS TA Value Min 4.5 3.0 0.022 -40 Typ 5.0 0.1 Max 5.5 5.5 1.0 +105 Unit V V F C
(VSS = AVSS = 0.0 V) Remarks Under normal operation Retains status at the time of operation stop *
Power supply voltage Smoothing capacitor Operating temperature
* : Use a ceramic capacitor or capacitor of better AC characteristics. Capacitor at the VCC should be greater than this capacitor. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
* C pin connection circuit
C
CS
36
MB90440G Series
3. DC Characteristics
Parameter Symbol VIHS VIHA VIH VIHM VILS VILA VIL VILM Output H voltage Output L voltage Input leak current VOH VOL IIL Pin CMOS Hysteresis input pin AUTOMOTIVE input pin TTL input pin MD input pin CMOS Hysteresis input pin AUTOMOTIVE input pin TTL input pin MD input pin All output pins All output pins
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Value Condition Unit Remarks Min Typ Max VCC = 4.5 V, IOH = -4.0 mA VCC = 4.5 V, IOL = 4.0 mA VCC = 5.5 V, VSS < VI < VCC 0.8 VCC 0.8 VCC 2.0 VCC - 0.3 VSS - 0.3 VSS - 0.3 VCC - 0.5 -5 VCC + 0.3 VCC + 0.3 0.2 VCC 0.5 VCC 0.8 VSS + 0.3 0.4 +5 V V V V V V V V V V A
Input H voltage
Input L voltage
(Continued)
37
MB90440G Series
(Continued)
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Symbol Pin Condition VCC = 5.0 V Internal frequency : 16 MHz, At normal operating ICC VCC = 5.0 V Internal frequency : 16 MHz, At flash programming / erasing VCC = 5.0 V Internal frequency : 16 MHz, At sleep VCC = 5.0 V Internal frequency : 8 kHz, At sub operation TA = + 25 C VCC = 5.0 V Internal frequency : 8 kHz, At sub sleep TA = + 25 C VCC = 5.0 V Internal frequency : 8 kHz, At watch mode TA = + 25 C VCC = 5.0 V Internal frequency : 2 MHz, At timer base timer mode TA = + 25 C At stop mode, TA = + 25 C Other than AVCC, AVSS, AVRH, AVRL, C, VCC, VSS P00 to P07, P10 to P17, P20 to P27, P30 to P37, RST MD2 Value Min Typ 45 Max 60 Unit Remarks
Parameter
mA
50
70
mA
ICCS
13
22
mA MB90443G (under development) MB90F443G
ICCL Power supply current* ICCLS VCC

50 300
100 500
A A A
15
40
ICCT
7
25
A
ICTS

600 1200
A A
ICCH
5
20
Input capacity
CIN
10
15
pF
Pull-up resistance
RUP
25
50
100
k
Pull-down resistance
RDOWN
25
50
100
k
* : The power supply current is measured with an external clock.
38
MB90440G Series
4. AC Characteristics
(1) Clock Timing (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Value Unit Remarks Min Typ Max 3 62.5 10 1.5 62.5 32.768 30.5 15.2 8.192 122.1 16 333 5 16 666 MHz kHz ns s ns s ns Duty ratio is about 30% to 70%. When using external clock
Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rise and fall time Internal operating clock frequency Internal operating clock cycle time
Symbol fC fCL tCYL tLCYL PWH, PWL PWLH, PWLL tCR, tCF fCP fLCP tCP tLCP
Pin X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0
MHz When using main clock kHz When using sub-clock ns s When using main clock When using sub-clock
* Clock Timing
tCYL
X0
PWH tCF tLCYL PWL tCR
0.8 VCC 0.2 VCC
X0A
PWLH tCF PWLL tCR
0.8 VCC 0.2 VCC
39
MB90440G Series
* Guaranteed PLL operation range Relationship between internal operation clock frequency and power supply voltage
Guaranteed operation range 5.5 Power supply voltage VCC (V)
4.5
Guaranteed PLL operation range
1.5
8 Internal clock fCP (MHz)
16
Relationship between oscillation frequency and internal operating clock frequency
16 Internal clock fCP (MHz) x4 x3 x2 x1
12 9 8 Not multiplied
4
3
4
8 Oscillation frequency fC (MHz)
16
The AC ratings are measured for the following measurement reference voltages. * Input signal waveform CMOS Hysteresis Input Pin
0.8 VCC 0.2 VCC
* Output signal waveform Output Pin
2.4 V 0.8 V
TTL Input Pin
2.0 V 0.8 V
AUTOMOTIVE Input Pin
0.8 VCC 0.5 VCC
40
MB90440G Series
(2) Clock Output Timing
Parameter Cycle time CLK CLK
Symbol tCYC tCHCL
Pin CLK
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Value Condition Unit Remarks Min Max VCC = 5 V 10% 62.5 20 ns ns
tCYC tCHCL 2.4 V 2.4 V 0.8 V
CLK
41
MB90440G Series
(3) Reset Input Timing and Hardware Stand-by Input Timing (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Value Parameter Symbol Pin Unit Remarks Min Max 16 tCP Reset input time tRSTL RST Oscillation time of oscillator + 100 s + 16 tCP ns Under normal operation In stop mode, watch mode, sub-clock mode, sub-sleep mode
Note: * Oscillator oscillation time is the time that amplitude reached 90%. For a crystal oscillator, the oscillation time is between several ms to tens of ms; for a FAR/ceramic oscillator, the oscillation time is between hundreds of s to several ms, and for an external clock the oscillation time is 0 ms. * Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm. * Under normal operation :
tRSTL
RST
0.2 VCC 0.2 VCC
* In stop mode :
tRSTL
RST
0.2 VCC 90% of amplitude 0.2 VCC
X0
Internal operation clock
Oscillator oscillation time
100 s + 16 tCP
Oscillation setting time
Instruction execution
Internal reset
42
MB90440G Series
(4) Power-on Reset
Parameter Power supply rising time Power supply cut-off time
Symbol tR tOFF
Pin VCC VCC
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Value Condition Unit Remarks Min Max 0.05 50 30 ms ms * Due to repeated operations
* : VCC must be kept lower than 0.2 V before power-on. Note : The above values are used for causing a power-on reset. Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn the power supply on using the above values.
tR 2.7 V 0.2 V 0.2 V tOFF 0.2 V
VCC
Sudden changes in the power supply voltage may cause a power on reset. We recommend to raise the voltage smoothly to suppress fluctuation during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL clock.
VCC 3V VSS
RAM data Hold
We recommend rising speed of the supply voltage at 50 mV/ms or slower
43
MB90440G Series
(5) Bus Timing (Read)
Parameter ALE pulse width Valid address ALE time ALE Address valid time Valid address RD time Valid address Valid data input RD pulse width RD Valid data input RD Data hold time RD ALE time RD Address valid time Valid address CLK time RD CLK time ALE RD time
Symbol tLHLL tAVLL tLLAX
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = -40 C to +105 C) Value Pin Unit Remarks Min Max ALE ALE, A16 to A23, AD00 to AD15 ALE, AD00 to AD15 A16 to A23, AD00 to AD15, RD A16 to A23, AD00 to AD15 RD RD, AD00 to AD15 RD, AD00 to AD15 RD, ALE RD, A16 to A23 A16 to A23, AD00 to AD15, CLK RD, CLK ALE, RD tCP / 2 - 20 tCP / 2 - 20 tCP / 2 - 15 tCP - 15 3 tCP / 2 - 20 0 tCP / 2 - 15 tCP / 2 - 10 tCP / 2 - 20 tCP / 2 - 20 tCP / 2 - 15 5 tCP / 2 - 60 3 tCP / 2 - 60 ns ns ns
tAVRL
ns
tAVDV tRLRH tRLDV tRHDX tRHLH tRHAX tAVCH tRLCH tLLRL
ns ns ns ns ns ns ns ns ns
44
MB90440G Series
* Bus Timing (Read)
tAVCH 2.4 V
tRLCH 2.4 V
CLK
tAVLL tLLAX 2.4 V tLHLL tAVRL 0.8 V tRLRH 2.4 V 0.8 V tLLRL tRHAX 2.4 V 2.4 V 0.8 V tAVDV tRLDV tRHDX 2.4 V Address 0.8 V 0.8 V 0.2 VCC 0.8 VCC Read data 0.2 VCC 0.8 VCC tRHLH 2.4 V
ALE
2.4 V
RD
A23 to A16
0.8 V
AD15 to AD00
2.4 V
45
MB90440G Series
(6) Bus Timing (Write)
Parameter
Symbol
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = -40 C to +105 C) Value Pin Unit Remarks Min Max A16 to A23, AD00 to AD15, WR WR AD00 to AD15, WR AD00 to AD15, WR A16 to A23, WR WR, ALE WR, CLK tCP - 15 3 tCP / 2 - 20 3 tCP / 2 - 20 20 tCP / 2 - 10 tCP / 2 - 15 tCP / 2 - 20 ns ns ns ns ns ns ns
Valid address WR time WR pulse width Valid data output WR time WR Data hold time WR Address valid time WR ALE time WR CLK time * Bus Timing (Write)
tAVWL tWLWH tDVWH tWHDX tWHAX tWHLH tWLCH
tWLC 2.4 V
CLK
tWHL 2.4 V
ALE
tAVWL tWLWH 2.4 V 0.8 V
WR (WRL, WRH)
tWHAX 2.4 V 2.4 V 0.8 V tDVWH tWHDX 2.4 V Write data 0.8 V 0.8 V
A23 to A16
0.8 V
AD15 to AD00
2.4 V Address 0.8 V
2.4 V
46
MB90440G Series
(7) Ready Input Timing
Parameter RDY setup time RDY hold time
Symbol tRYHS tRYHH
Pin RDY RDY
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = -40 C to +105 C) Value Unit Remarks Min Max 45 0 ns ns
Note : If the RDY setup time is insufficient, use the auto-ready function. * Ready Input Timing
2.4 V
CLK
ALE
RD/WR
tRYHS
tRYHH 0.8 VCC
RDY no WAIT is used. RDY When WAIT is used (1 cycle).
0.8 VCC
0.2 VCC
47
MB90440G Series
(8) Hold Timing
Parameter Pin floating HAK time HAK Pin valid time
Symbol tXHAL tHAHV
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = -40 C to +105 C) Value Pin Unit Remarks Min Max HAK HAK 30 tCP tCP 2 tCP ns ns
Note : More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched. * Hold Timing
HAK
0.8 V tXHAL tHAHV High impedance 2.4 V 0.8 V 2.4 V
Each pin
2.4 V 0.8 V
48
MB90440G Series
(9) UART0/1, Serial I/O Timing
Parameter Serial clock cycle time
Symbol tSCYC
Pin SCK0 to SCK2 SCK0 to SCK2, SOT0 to SOT2 SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2 SCK0 to SCK2 SCK0 to SCK2, SOT0 to SOT2 SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = -40 C to +105 C) Value Condition Unit Remarks Min Max 8 tCP ns
SCK SOT delay time
tSLOV
Valid SIN SCK
tIVSH
An output pin of internal sift clock mode CL = 80 pF + 1 TTL.
-80
+80
ns
100
ns
SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width
tSHIX
60

ns
tSHSL tSLSH
4 tCP 4 tCP
ns ns
SCK SOT delay time
tSLOV
An output pin of external sift clock mode CL = 80 pF + 1 TTL.
150
ns
Valid SIN SCK
tIVSH
60
ns
SCK valid SIN hold time
tSHIX
60
ns
Notes : * AC ratings in CLK synchronous mode. * CL is load capacitance value connected to pins when testing.
49
MB90440G Series
* Internal Shift Clock Mode
tSCYC 2.4 V 0.8 V tSLOV 2.4 V 0.8 V
SCK
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
* External Shift Clock Mode
tSLSH 0.2 VCC tSLOV 2.4 V 0.2 VCC tSHSL 0.8 VCC
SCK
0.8 VCC
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
50
MB90440G Series
(10) Timer Related Resource Input Timing
Parameter Input pulse width
Symbol tTIWH tTIWL
Pin TIN0, TIN1 IN0 to IN7
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = -40 C to +105 C) Value Condition Unit Remarks Min Max 4 tCP ns
* Timer Input Timing
0.8 VCC TIN0, TIN1 IN0 to IN7 0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC
51
MB90440G Series
(11) Timer Related Resource Output Timing
Parameter CLK TOUT transition time
Symbol tTO
Pin TOT0 to TOT1, PPG0 to PPG3
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = -40 C to +105 C) Value Condition Unit Remarks Min Max 30 ns
* Timer Output Timing
CLK
2.4 V
TOUT
tTO
2.4 V 0.8 V
(12) Trigger Input Timing
Parameter Input pulse width
Symbol tTRGH tTRGL
Pin INT0 to INT7, ADTG
(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = -40 C to +105 C) Value Condition Unit Remarks Min Max 5 tCP 1 ns s normal operation stop mode
* Trigger Input Timing
0.8 VCC INT0 to INT7 ADTG
0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC
52
MB90440G Series
5. A/D Converter
* Electrical Characteristics (VCC = AVCC = 5.0 V 10%, VSS = AVSS = 0.0 V, 3.0 V AVRH - AVRL, TA = -40 C to +105 C) Value Parameter Symbol Pin Unit Remarks Min Typ Max Resolution Total error Nonlinearity error Differential linearity error Zero transition voltage Full scale transition voltage Compare time Sampling time Analog port input current Analog input voltage VOT VFST IAIN VAIN Reference voltage Power supply current Reference voltage supply current Offset between channels IA IAH IR IRH AVRL AVCC AVCC AVRH AVRH AN0 to AN7 AN0 to AN7 AN0 to AN7 AN0 to AN7 AN0 to AN7 AVRH AVRL - 3.5 LSB AVRH - 6.5 LSB 66 tCP 32 tCP AVRL AVRL + 2.7 LSB 0 AVRL + 0.5 LSB AVRH - 1.5 LSB 2 0.9 10 5.0 2.5 1.9 AVRL + 4.5 LSB AVRH + 1.5 LSB 10 AVRH AVCC AVRH - 2.7 LSB 6 5 1.3 5 4 bit LSB LSB LSB V V ns ns A V V V mA A mA A LSB * * 1 LSB = (AVRH - AVRL) / 1024 [V] Machine clock of 16 MHz
* : Specifies the power supply current (VCC = AVCC = AVRH = 5.0 V) when the A/D converter is inactive and the CPU has been stopped.
53
MB90440G Series
* A/D Converter Glossary
Resolution Linearity error : Analog changes that are identifiable with the A/D converter : The deviation of the straight line connecting the zero transition point ( "00 0000 0000" to "00 0000 0001" ) with the full-scale transition point ( "11 1111 1110" to "11 1111 1111" ) from actual conversion characteristics. : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value. : The difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error, and linearity error.
Differential linearity error Total error
Total error
3FF 3FE 3FD Digital output {1 LSB x (N - 1) + 0.5 LSB} Actual conversion characteristics 1.5 LSB
004 003 002 001 0.5 LSB AVRL Analog input
VNT (measured value) Actual conversion characteristics Theoretical characteristics
AVRH
Total error of digital output N =
VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB 1 LSB = (theoretical value) AVRH - AVRL [V] 1024 VOT (theoretical value) = AVRL + 0.5 LSB [V] VFST (theoretical value) = AVRH - 1.5 LSB [V] VNT : The voltage at a transition of digital output from (N - 1) to N.
[LSB]
(Continued)
54
MB90440G Series
(Continued)
Linearity error
3FF 3FE 3FD Digital output Actual conversion characteristics {1 LSB x (N - 1) + VOT } N+1 VFST (measured value) VNT (measured value) Actual conversion characteristics Actual conversion characteristics
Differential linearity error
Theoretical characteristics
Digital output
N
004 003 002
N-1
V (N + 1) T (measured value) VNT (measured value) Actual conversion characteristics AVRH Analog input
Theoretical characteristics 001 VOT (measured value) AVRL Analog input AVRH
N-2
AVRL
Linearity error of digital output N = Differential linearity error of digital output N = 1 LSB =
VNT - {1 LSB x (N - 1) + VOT} 1 LSB V (N+1) T - VNT 1 LSB VFST - VOT 1022 -1 LSB [LSB] [V]
[LSB]
VOT : Voltage at transition of digital output 000H to 001H. VFST : Voltage at transition of digital output 3FEH to 3FFH.
55
MB90440G Series
* Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions : Output impedance values of the external circuit of about 5 k or lower are recommended. If external capacitors are used, a capacitance of several thousand times the internal capacitor value is recommended in order to minimize the effect of voltage distribution between the external and internal capacitor. Note: If the output impedance of the external circuit is too high, the sampling time for analog voltages may not be sufficient (sampling period = 2.00 s @ machine clock of 16 MHz) . The output impedance of the external circuit can be set to approx. 15k or lower , when the sampling period is set to 4.00 s. * Analog Input Circuit Model
Comparator Analog input R C
MB90F443G, MB90V440G MB90443G (Under development)
R = 3.2 k, : C = 30 pF : R = 2.6 k, : C = 28 pF :
* About Error The smaller the absolute value of | AVRH - AVRL | is, the greater the relative error is.
6. Flash Memory Program/Erase Characteristics
Parameter Sector erase time Chip erase time Word (16 bit width) programming time Erase/Program cycle TA = + 25 C VCC = 5.0 V Condition Value Min 10,000 Typ 1 5 16 Max 15 3,600 Unit s s s cycle Remarks Excludes 00H programming prior erasure Excludes 00H programming prior erasure Excludes system-level overhead
56
MB90440G Series
s EXAMPLE CHARACTERISTICS
* "H" Level Output Voltage * "L" Level Output Voltage
VOH - IOH
(Vcc = 4.5 V, Ta = +25C) 4.5 4 3.5 3 2.5 2 0.3 1.5 1 0.5 0 0.0 -2.0 -4.0 -6.0 -8.0 -10.0 0.2 0.8
VOL - IOL
(VCC = 4.5 V, Ta = +25C)
0.7
0.6
VOH [V]
VOL [mV]
0.5
0.4
0.1
0 0.0
2.0
4.0
6.0
8.0
10.0
IOH [mA]
IOL [mA]
57
MB90440G Series
* Power Supply Current (FLASH)
Icc - Vcc
(Ta = +25C) 50 fcp = 16 MHz 45 40 fcp = 12 MHz 35
14 18 16 20
Iccs - Vcc
(Ta = +25C) fcp = 16 MHz
fcp = 12 MHz fcp = 10 MHz fcp = 8 MHz
Icc [mA]
25 20 15 10 5 0 2.0
fcp = 8 MHz
Iccs [mA]
30
fcp = 10 MHz
12 10 8
fcp = 4 MHz fcp = 2 MHz
6 4 2 0 2.0
fcp = 4 MHz fcp = 2 MHz
3.0
4.0
5.0
6.0
7.0
3.0
4.0
5.0
6.0
7.0
Vcc [V]
Vcc [V]
ICTS - VCC
600 (fcp = 2 MHz, Ta = +25C) 20 18 500 16 400 14
ICCH - VCC
(Ta = +25C)
ICTS [ A]
300
ICCT [ A]
2.0 3.0 4.0 5.0 6.0 7.0
12 10 8
200 6 100 4 2 0 0 2.0 3.0 4.0 5.0 6.0 7.0
Vcc [V] Vcc [V]
58
MB90440G Series
s ORDERING INFORMATION
Part number MB90443GPF (under development) MB90F443GPF MB90V440GCR Package 100-pin Plastic QFP (FPT-100P-M06) 256-pin Ceramic PGA (PGA-256C-A01) For evaluation Remarks
59
MB90440G Series
s PACKAGE DIMENSIONS
100-pin Plastic QFP (FPT-100P-M06)
23.900.40(.941.016) 20.000.20(.787.008)
80 51
Note : Pins width and pins thickness include plating thickness.
81
50
0.10(.004) 17.900.40 (.705.016) 14.000.20 (.551.008) INDEX Details of "A" part
100 31
1
30
0.25(.010) +0.35 3.00 -0.20 +.014 .118 -.008 (Mounting height) 0~8 0.170.06 (.007.002) 0.800.20 (.031.008) 0.880.15 (.035.006) 0.250.20 (.010.008) (Stand off)
0.65(.026)
0.320.05 (.013.002)
0.13(.005)
M
"A"
C
2001 FUJITSU LIMITED F100008S-c-4-4
Dimensions in mm (inches)
60
MB90440G Series
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0204 (c) FUJITSU LIMITED Printed in Japan

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